发明名称 |
Scheduling the dispatch of cells in non-empty virtual output queues of multistage switches using a pipelined arbitration scheme |
摘要 |
A pipeline-based matching scheduling approach for input-buffered switches relaxes the timing constraint for arbitration with matching schemes, such as CRRD and CMSD. In the new approach, arbitration may operate in a pipelined manner. Each sub-scheduler is allowed to take more than one time slot for its matching. Every time slot, one of them provides a matching result(s). The sub-scheduler can use a matching scheme such as CRRD and CMSD.
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申请公布号 |
US6940851(B2) |
申请公布日期 |
2005.09.06 |
申请号 |
US20010911044 |
申请日期 |
2001.07.23 |
申请人 |
POLYTECHNIC UNIVERSITY |
发明人 |
OKI EIJI;CHAO HUNG-HSIANG JONATHAN;ROJAS-CESSA ROBERTO |
分类号 |
H04L12/56;H04Q11/04;(IPC1-7):H04L12/50;H04Q11/00 |
主分类号 |
H04L12/56 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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