发明名称 |
Feed forward sigma delta interpolator for use in a fractional-N synthesizer |
摘要 |
A sigma delta interpolator for use in a fractional N synthesizer having a multi-modulus divider for controlling the output frequency of the synthesizer. The sigma delta interpolator includes an accumulator operative for receiving an input signal representing the desired frequency output of the fractional N synthesizer and for generating a digital output signal having M bits, which include N most significant bits and n least significant bits. The N most significant bits output by the accumulator are coupled to the multi-modulus divider and are operative for controlling the operation of the multi-modulus divider. The sigma delta interpolator further includes a delay circuit coupled to the accumulator, which functions to receive the n least significant bits and implement a delay function defined by equation: 1-(1-Z<SUP>-1</SUP>)<SUP>N</SUP>, where N corresponds to the order of the sigma delta interpolator.
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申请公布号 |
US6941330(B2) |
申请公布日期 |
2005.09.06 |
申请号 |
US20010963350 |
申请日期 |
2001.09.26 |
申请人 |
HUGHES ELECTRONICS CORPORATION |
发明人 |
JACKSON THOMAS;EAPEN GEORGE;DAI FOSTER |
分类号 |
H03L7/197;(IPC1-7):G06F1/02 |
主分类号 |
H03L7/197 |
代理机构 |
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