发明名称 |
Apparatus and a method to adjust signal timing on a memory interface |
摘要 |
An apparatus and a method for adjusting signal timing in a memory interface have been disclosed. One embodiment of the apparatus includes a number of slave delay lock loops (DLLs) in a memory interface to adjust timing between a number of signals to compensate for timing skew, and a number of input/output (I/O) buffers to output the adjusted signals to one or more memory devices coupled to the memory interface. Other embodiments are described and claimed.
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申请公布号 |
US2005190193(A1) |
申请公布日期 |
2005.09.01 |
申请号 |
US20040791180 |
申请日期 |
2004.03.01 |
申请人 |
FREKER DAVID E.;BOGIN ZOHAR;NAVNEET DOUR;MUKKER ANOOP;TRIEU TUONG P. |
发明人 |
FREKER DAVID E.;BOGIN ZOHAR;NAVNEET DOUR;MUKKER ANOOP;TRIEU TUONG P. |
分类号 |
G06F13/00;G06F13/16;G06F13/372;(IPC1-7):G06F13/00 |
主分类号 |
G06F13/00 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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