Delay time verifying method with less processing load

摘要

In a method of verifying a delay time of a target circuit section, a first determination of a shortest of short delay times of each of components of the target circuit section in two or more temperature conditions is carried out. A second determination of a longest one of long delay times of each of the components of the target circuit section in two or more temperature conditions is carried out. Then, a first summation of the shortest delay times of the components is calculated and a second summation of the longest delay times of the components is calculated. Then, whether each of the first and second summations satisfy a predetermined timing constraint is verified.