摘要 |
<p>To produce a contact hole plane, in a memory component, a semiconductor substrate (10) is prepared with a cell field zone (101) and a logic zone (102) together with surface gate electrode conductor paths (11,12) under a covering layer (113,123), and an oxide layer (13) is applied. A block mask (14) at the cell fields is used for anisotropic etching of the oxide layer to free the semiconductor surface and covering layer at the logic zone, and the mask is removed. A second oxide layer is applied forming a sacrifice layer over the conductor paths, and a mask layer is deposited and structured to give openings for the bit conductor contacts for the contact openings. An anisotropic etching of the sacrifice layer forms blocks over the contact openings and the mask layer is removed. Etching of the conductor paths and semiconductor surface at the blocks gives them side covers from the two oxide layers. A filling layer is between the blocks, the sacrifice layer blocks are removed at the filling layer, and the contact openings are filled with a conductive material.</p> |