发明名称 |
System and method for achieving low power standby and fast relock for digital phase lock loop |
摘要 |
A digital phase lock loop (DPLL) system and method employ digital loop control and a digital controller to drive the DPLL oscillator with fast re-lock capability. The DPLL optionally uses low power retention flops to implement low power and fast interrupt services.
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申请公布号 |
US2005189972(A1) |
申请公布日期 |
2005.09.01 |
申请号 |
US20040788709 |
申请日期 |
2004.02.27 |
申请人 |
FOO TIM;HAROUN BAHER S.;MAIR HUGH T. |
发明人 |
FOO TIM;HAROUN BAHER S.;MAIR HUGH T. |
分类号 |
H03L7/06;H03L7/08;H03L7/099;(IPC1-7):H03L7/06 |
主分类号 |
H03L7/06 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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