| 摘要 |
<p>A redundancy judgment circuit (3) includes: an in-redundancy judgment circuit address incrementing controller (30); an even-number redundant address judgment unit (31); an odd-number redundant address judgment unit (32); a redundant address ROM (33), a redundant IOROM (34), and a selection unit (35). By building the redundancy judgment circuit (3) for 2-bit pre-fetch operation shown in Fig. 2 into a circuit (memory cell circuit (2), read out circuit (4), address generation circuit (5)) for 2-bit pre-fetch operation shown in Fig. 1, it is possible to give aid to redundancy even in the burst operation by the 2-bit pre-fetch and prevent lowering of the read out operation speed. Moreover, it becomes possible to reduce the wiring length of the decode signal bus in the column direction substantially by half and reduce the decode signal bus region substantially by half. Accordingly, it is possible to prevent danger of increase of wiring density in the wiring region of the decode signal bus and increase the read out speed.</p> |
