HIGH-SPEED TEST CYCLE COUNTER

摘要

A high-speed wide range counter for Automated Test Equipment applications is divided into two separate, parallel counting blocks for counting over a wide range of count values including short and minimum counts while optimizing gate utilization. The first counting block based on pipeline logic circuitry is used to perform lo ng counts and the second counting block based on wide parallel logic circuitry is used to perform short counts. The two blocks operate one at a time, exclusively of each other. The ir outputs are combined to provide a final count value. The overall counter is optimize d for high speeds as required in today's ATE applications since the combinatorial logic delay with polynomial counter decoding stages is avoided in the case of short count values. The counter also supports loading on a cycle-by-cycle basis.