发明名称 |
Method and apparatus for designing semiconductor integrated circuit device based on voltage drop distribution |
摘要 |
A method for designing a semiconductor integrated circuit device for connecting between terminals of transistors formed on a silicon wafer by metal wiring. The method includes a first step of carrying out a schematic arrangement so as to minimize a distance of a wiring for connecting between the transistors or wiring capacitance based on input information on transistors; a second step of producing information on a voltage drop value based on the schematic arrangement of the transistors; and a third step of arranging the transistors based on the information on a voltage drop value.
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申请公布号 |
US6938233(B2) |
申请公布日期 |
2005.08.30 |
申请号 |
US20030637254 |
申请日期 |
2003.08.08 |
申请人 |
MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD. |
发明人 |
SATOH KAZUHIRO;IWANISHI NOBUFUSA;ISHIBASHI NORIKO |
分类号 |
G06F17/50;(IPC1-7):G06F17/50 |
主分类号 |
G06F17/50 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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