发明名称 Cache-line reuse-buffer
摘要 A method, apparatus, and system that compares a current fetch request having a first start address and length associated with the current fetch request to a second start address of the next fetch request, determines whether the content already loaded in a buffer will be used to at least partially fulfill the next fetch request based upon the comparison, and inhibits access to an instruction cache based upon the comparison.
申请公布号 US6938126(B2) 申请公布日期 2005.08.30
申请号 US20020121524 申请日期 2002.04.12
申请人 INTEL CORPORATION 发明人 RAMIREZ ALEJANDRO;GROCHOWSKI EDWARD;WANG HONG;SHEN JOHN
分类号 G06F9/38;G06F12/08;(IPC1-7):G06F12/00 主分类号 G06F9/38
代理机构 代理人
主权项
地址