发明名称 |
Method, apparatus, and system for hardware design and synthesis |
摘要 |
According to one embodiment of the present invention, a method and system for VLSI hardware design and synthesis is provided in which components provided by a heterogeneous modeling framework are interconnected, based on design specifications of a VLSI, to create a corresponding behavioral VLSI model. The heterogeneous modeling framework contains a first component library including logic functions that can be used to build hardware structural models and a second component library including numeric standard. The created model is simulated, tested, and functionally verified using discrete event domain simulation capabilities provided by the heterogeneous framework. A corresponding structural model is extracted from the tested behavioral VLSI model using a software tool provided by the heterogeneous modeling framework.
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申请公布号 |
US6938237(B1) |
申请公布日期 |
2005.08.30 |
申请号 |
US20020184799 |
申请日期 |
2002.06.28 |
申请人 |
ELLIPSIS DIGITAL SYSTEMS, INC. |
发明人 |
EL-GHOROURY HASSAN N. |
分类号 |
G06F17/50;(IPC1-7):G06F17/50 |
主分类号 |
G06F17/50 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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