发明名称 |
High density SRAM cell with latched vertical transistors |
摘要 |
High density static memory cells and arrays containing gated lateral bipolar transistors which can be latched in a bistable on state. Each transistor memory cell includes two gates which are pulse biased during the write operation to latch the cell. Also provided is a CMOS fabrication process to create the cells and arrays.
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申请公布号 |
US6936886(B2) |
申请公布日期 |
2005.08.30 |
申请号 |
US20000750111 |
申请日期 |
2000.12.29 |
申请人 |
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发明人 |
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分类号 |
G11C11/41;H01L27/11;(IPC1-7):H01L29/76;H01L29/788 |
主分类号 |
G11C11/41 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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