发明名称 Error detection system for a FIFO memory
摘要 An error detection system for detecting errors in data output from a FIFO memory includes a first CRC generator for receiving an inbound data stream and generating a first CRC value based on a data block in the inbound data stream. A device coupled to the first CRC generator selectively inputs the data block and the first CRC value into the FIFO. A second CRC generator generates a second CRC value based on the data block after being output from the FIFO in an outbound data stream. The second CRC value indicates whether the data block contains an error.
申请公布号 US6938201(B2) 申请公布日期 2005.08.30
申请号 US20020235060 申请日期 2002.09.05
申请人 AGILENT TECHNOLOGIES, INC. 发明人 GOYINS GREGG S.;AYALASOMAYAJULA NARAYAN R.
分类号 G06F12/16;G06F11/10;H03M13/09;(IPC1-7):G11C29/00 主分类号 G06F12/16
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