发明名称 Integrated circuit testing method and system
摘要 A system for testing an integrated circuit, the integrated circuit including: flip-flops connected to a logic block and the test system including circuitry for connecting the flip-flops as a register, circuitry for inhibiting the different elements of the logic block capable of disturbing the sequencing of the register or the propagation of the signals into the logic block, and a control circuit for separately controlling the different inhibiting circuits and the circuitry for connecting the flip-flops as a register.
申请公布号 US6938194(B2) 申请公布日期 2005.08.30
申请号 US20020083714 申请日期 2002.02.26
申请人 STMICROELECTRONICS S.A. 发明人 PRUNIER JACQUES
分类号 G01R31/3185;(IPC1-7):G01R31/28 主分类号 G01R31/3185
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