| 摘要 |
A circuit (10) and method for expanding the pulse width of a signal (20) based on the input signal's (18) pulse width. A circuit (10) generates a delay equal to the pulse width of the input signal ((18) for both a SHIFT (52) and OUT (20) signal, which are out of phase with each other. The delay is generated when a capacitor (16) applies voltage to two control transistors in both the SHIFT (12) and OUT (14) blocks, reducing gate control in these transistors and generating a delay in the falling edge of these signals such that the pulse width of the SHIFT signal (52) is reduced and the pulse width of the OUT signal (20) is increased. The capacitor (16) is charged by a transistor (22) activated by the SHIFT signal (52). The pulse-doubling system is self-converging: when the SHIFT signal's (52) pulse width is zero, the OUT signal's (20) pulse width is doubled, and the capacitor's (16) charging level is fixed since it is no longer charged by the transistor (22) controlled by the SHIFT signal. The circuit (10) may be modified so that the output signal's (20) pulse width is a known factor of multiplication wider than the input signal's (18) pulse width.
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