| 摘要 |
<p>Provided are a delay stage and a delay circuit that are insensitive to an operating voltage and have a constant delay time irrespective of a time interval between input signal pulses. The delay stage includes a first inverter that inverts an input signal, a first capacitor having one end connected to a first voltage node, a first switch that is connected between the other end of the first capacitor and an output terminal of the first inverter and is turned on in response to a control signal, a second inverter that inverts an output signal of the first inverter, a second capacitor having one end connected to a second voltage node, and a second switch that is connected between the other end of the second capacitor and an output terminal of the second inverter and is turned on in response to an inverted signal of the control signal.</p> |
