发明名称 Improvements relating to frequency and/or phase lock loops
摘要 A control loop (10) for producing an output signal with a stable nominal frequency is provided. The control loop includes inputs for reference (11) and oscillator (25) output signals, a beat frequency generator (12) for producing a signal with a frequency that is the difference between the oscillator and reference signal frequencies, an ADC (14) to convert the beat frequency to a digital beat frequency signal, an estimator (17) for estimating the frequency or phase of the beat signal, an adder (18) for combining an offset and modulation signal and the estimated frequency or phase of the beat signal into an added signal, and a DAC (23) for generating an analogue control signal for controlling the oscillator output frequency.
申请公布号 NZ524537(A) 申请公布日期 2005.08.26
申请号 NZ20030524537 申请日期 2003.03.04
申请人 TAIT ELECTRONICS LIMITED 发明人 SIDDALL, WILLIAM MARK
分类号 H03C3/09;H03L7/185;(IPC1-7):H03C3/09;H03L7/083;H03L7/02 主分类号 H03C3/09
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