发明名称 |
CIRCUIT FOR ACCURATE MEMORY READ OPERATIONS |
摘要 |
A memory circuit arrangement for sensing current in a target cell (305) during a read operation is disclosed. According to one exemplary embodiment, the memory circuit arrangement comprises the target cell (305) and a first neighboring cell (355) adjacent to the target cell (305). The first target cell (305) has a first bit line (316) connected to ground (365); the target cell (305) also has a second bit line (321) connected to a sensing circuit (360). The first neighboring cell (355) shares the second bit line (321) with the target cell (305); the first neighboring cell (355) also has a third bit line (341) connected to the sensing circuit (360) during the read operation. The memory circuit arrangement results in increased error margins in a fast and accurate manner during the read operation of the target cell (305).
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申请公布号 |
KR20050084090(A) |
申请公布日期 |
2005.08.26 |
申请号 |
KR20057009918 |
申请日期 |
2003.07.24 |
申请人 |
ADVANCED MICRO DEVICES, INC. |
发明人 |
LE BINH Q.;ACHTER MICHAEL;CLEVELAND LEE |
分类号 |
G11C16/04;G11C16/26;(IPC1-7):G11C16/26 |
主分类号 |
G11C16/04 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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