发明名称 |
Methods of fabricating semiconductor integrated circuits using selective epitaxial growth and partial planarization techniques and semiconductor integrated circuits fabricated thereby |
摘要 |
Methods of fabricating a semiconductor integrated circuit having thin film transistors using an SEG technique are provided. The methods include forming an inter-layer insulating layer on a single-crystalline semiconductor substrate. A single-crystalline semiconductor plug extends through the inter-layer insulating layer, and a single-crystalline epitaxial semiconductor pattern is in contact with the single-crystalline semiconductor plug on the inter-layer insulating layer. The single-crystalline epitaxial semiconductor pattern is at least partially planarized to form a semiconductor body layer on the inter-layer insulating layer, and the semiconductor body layer is patterned to form a semiconductor body. As a result, the semiconductor body includes at least a portion of the single-crystalline epitaxial semiconductor pattern. Thus, the semiconductor body has an excellent single-crystalline structure. Semiconductor integrated circuits fabricated using the methods are also provided.
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申请公布号 |
US2005184292(A1) |
申请公布日期 |
2005.08.25 |
申请号 |
US20050065750 |
申请日期 |
2005.02.24 |
申请人 |
SAMSUNG ELECTRONICS CO., LTD. |
发明人 |
KWAK KUN-HO;JANG JAE-HOON;JUNG SOON-MOON;CHO WON-SEOK;LIM HOON;KIM SUNG-JIN;HWANG BYUNG-JUN;KIM JONG-HYUK |
分类号 |
H01L21/8244;H01L27/108;H01L27/11;(IPC1-7):H01L27/108 |
主分类号 |
H01L21/8244 |
代理机构 |
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地址 |
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