| 摘要 |
<p><P>PROBLEM TO BE SOLVED: To provide nonvolatile semiconductor core memory performance which is reinforced by reducing stress on a core memory cell. <P>SOLUTION: The stress is reduced by selectively impressing a bias voltage to a read line 13 under the control of a word line 19. The word line is connected to an inverting element, and this element is connected to a transistor for grounding the gate of a variable threshold value transistor 11b at a memory cell 11. The synchronous power down of the read line is reflected with the power down of the word line. Further, in case of power down, a sense amplifier 29 for the specified core memory cell is disconnected from a master latch circuit 112, and that amplifier is connected to a slave latch circuit 114 for the purpose of guaranteeing data sensed by the core memory during a read operation and applies a preceding sense amplifier output to an I/O buffer 116. Moreover, a word line voltage during the erasing operation at the read line and the variable threshold value transistor is reduced. <P>COPYRIGHT: (C)2005,JPO&NCIPI</p> |
