| 摘要 |
PROBLEM TO BE SOLVED: To precisely evaluate delay time of a gate circuit or the like comprising small number of steps. SOLUTION: A first DLL circuit 10 outputs a delayed clock signal DCLK obtained, by delaying a reference clock signal REFCLK from one of a first delay step 16a. A second DLL circuit 30, comprising a second variable delay circuit 36 and a circuit to be evaluated 50 connected to the delay circuit 36, receives the delayed clock signal DCLK and outputs a second output clock signal OUT2, having the same phase as the reference clock signal REFCLK. A delay time T1 of the delay circuit 36 changes, according to an adjustment voltage V2 generated by a voltage generating circuit 34. When the period T of the reference clock signal REFCLK remains unchanged, and the sum of the delay time T1 and a delay time T2 of the circuit to be estimated 50 are always equal. Consequently, by monitoring the changes in the adjustment voltage V2, when the number of steps of circuit of the circuit to be estimated 50 is switched, the delay time of the circuit to be evaluated 50 is determined as the adjustment voltage V2. COPYRIGHT: (C)2005,JPO&NCIPI
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