发明名称 |
Multiplier-accumulator block mode splitting |
摘要 |
A programmable logic device is provided that includes a MAC block having mode splitting capabilities. Different modes of operation may be implemented simultaneously whereby the multipliers and other DSP circuitry of the MAC block may be allocated among the different modes of operation. For example, one multiplier may be used to implement a multiply mode while another two multipliers may be used to implement a sum of two multipliers mode.
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申请公布号 |
US2005187998(A1) |
申请公布日期 |
2005.08.25 |
申请号 |
US20040783820 |
申请日期 |
2004.02.20 |
申请人 |
ALTERA CORPORATION |
发明人 |
ZHENG LEON;LANGHAMMER MARTIN;PERRY STEVEN;METZGEN PAUL;STARR GREGORY;HWANG WILLIAM;THARMALINGAM KUMARA |
分类号 |
G06F7/544;G06F15/00;H03K19/177;(IPC1-7):G06F15/00 |
主分类号 |
G06F7/544 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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