发明名称 |
Saturation and rounding in multiply-accumulate blocks |
摘要 |
Saturation and rounding capabilities are implemented in MAC blocks to provide rounded and saturated outputs of multipliers and of add-subtract-accumulate circuitrs implemented using DSP. These features support any suitable format of value representation, including the x.15 format. Circuitry within the multipliers and the add-subtract-accumulate circuits implement the rounding and saturation features of the present invention.
|
申请公布号 |
US2005187999(A1) |
申请公布日期 |
2005.08.25 |
申请号 |
US20040783829 |
申请日期 |
2004.02.20 |
申请人 |
ALTERA CORPORATION |
发明人 |
ZHENG LEON;LANGHAMMER MARTIN;PERRY STEVEN;METZGEN PAUL;PRASAD NITIN;HWANG WILLIAM |
分类号 |
G06F7/52;(IPC1-7):G06F7/52 |
主分类号 |
G06F7/52 |
代理机构 |
|
代理人 |
|
主权项 |
|
地址 |
|