发明名称 Phase locked loop circuit
摘要 A PLL circuit for generating a clock signal synchronized with a first reference signal generated by superimposing a wobble signal on a land pre-pit signal or a second reference signal generated from a wobble signal. The PLL circuit enables reduction in circuit scale. When a DVD-R/RW is used as an optical disc, a first loop synchronizes the frequency of a wobble signal with the frequency of a divisional clock signal, which is generated from a recording clock signal of a voltage-controlled oscillator. Further, a second loop synchronizes the phase of the divisional clock signal with the phase of the LPP signal. When a DVD+R/RW is used as an optical disc, the first loop synchronizes the frequency of the divisional clock signal with the frequency of the wobble signal. Further, the second loop applies constant voltage to a control voltage input terminal of the voltage-controlled oscillator.
申请公布号 US6933790(B2) 申请公布日期 2005.08.23
申请号 US20040777481 申请日期 2004.02.12
申请人 SANYO ELECTRIC CO., LTD. 发明人 KIYOSE MASASHI;SHIRAISHI TAKUYA
分类号 G11B20/10;G11B7/005;G11B27/10;G11B27/19;G11B27/24;G11B27/30;H03K3/354;H03L7/08;H03L7/087;H03L7/089;H03L7/099;H03L7/107;(IPC1-7):H03L7/06 主分类号 G11B20/10
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