Use of a selective hard mask for the integration of double diffused drain MOS devices in deep sub-micron fabrication technologies

摘要

A process for integrating the fabrication of double diffused drain (DDD) MOSFET devices with the fabrication sub-micron CMOS devices, has been developed. The process features formation of an insulator hard mask shape on an underlying polysilicon gate structure shape in the DDD MOSFET region, while only a polysilicon gate structure shape is formed in the CMOS device region. High energy ion implantation procedures are employed to form the deep source/drain regions of the DDD MOSFET devices with the insulator hard mask shape preventing the high energy implantation procedure from disturbing the underlying channel region. An anneal procedure used activate and drive-in the implanted ions in the deep source/drain region of the DDD MOSFET device is followed by formation of the shallower source/drain regions of the sub-micron CMOS devices.