SIMULTANEOUS PLURAL CODE SERIES GENERATOR AND CDMA RADIO RECEIVER USING SAME

摘要

An EOR (XR11, XR12) of outputs from a plurality of shift stages S1, S2, S4 of an M-series generator 31A is formed, thereby obtaining an M-series which has a desired delay, which in an example is a three bit delay with respect to the output code from the generator 31A. Similarly, outputs from a plurality of shift stages are combined and an EOR thereof is formed to provide another delayed M-series. An EOR of each output from the simultaneously delayed code generator 31 and an output from other M-series generator 32 is formed, thus simultaneously obtaining a plurality of Gold code series.