| 摘要 |
An FPGA architecture has top, middle and low levels. The top level of the architecture is an array of the B16x16 tiles arranged in a rectangular array and enclosed by I/O blocks on the periphery. A B16x16 tile in the middle level of hierarchy is a sixteen by sixteen array of B 1 blocks. The B16x16 tile is a nesting of a B2x2 tile that includes a two by two array of four B 1 blocks. The routing resources in the middle level of hierarchy are expressway routing channels M 1 , M 2 , and M 3 including groups of interconnect conductors. The expressway routing channels M 1 , M 2 , and M 3 are segmented, and between each of the segments in the expressway routing channels M 1 , M 2 , and M 3 are disposed extensions that can extend the expressway routing channel M 1 , M 2 , or M 3 an identical distance along the same direction. The expressway routing channels M 1 , M 2 , and M 3 run both vertically through every column and horizontally through every row of B2x2 tiles. At the intersections of each of the expressway routing channels M 1 , M 2 , and M 3 in the horizontal direction with the expressway routing channels M 1 , M 2 and M 3 in the vertical direction is an expressway turn (E-turn) disposed at the center of each B2x2 tile. An E-turn is a passive device that includes a matrix of reprogrammable switches. The reprogrammable switches are preferably a pass device controlled by an SRAM bit. The interconnect conductors in the expressway routing channels M 1 , M 2 and M 3 that are fed into an E-turn may be coupled to many of the other interconnect conductors in the expressway routing channels M 1 , M 2 and M 3 that come into the E-turn by the programmable switches. Further, the interconnect conductors in the expressway routing channels M 1 , M 2 and M 3 that are fed into an E-turn continue in the same direction through the E-turn, even though the interconnect conductors are coupled to other interconnect conductors by the reprogrammable switches.
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