发明名称 PROCESSING SYSTEM, PROJECTOR AND MEMORY ACCESS CONTROL METHOD
摘要 PROBLEM TO BE SOLVED: To provide a processing system or the like allowing improvement of efficiency of access to a memory with a simple structure. SOLUTION: A subsystem 20 is connected to a main CPU 10 and the memory 30. The subsystem 20 includes: a host interface part 23 performing input/output with the main CPU 10; a memory interface part 21 performing input/output with the memory 30; a first bus 65 that is an output route to the host interface part 23 from the memory interface part 21; an internal register 22 temporarily storing a control parameter 32; a second bus 66 that is an output route to the internal register 22 from the memory interface part 21; a switching part 24 switching the bus such that the bus 65 or the bus 66 is used; and a control part 25 controlling the switching part 24 on the basis of a state of the subsystem 20. COPYRIGHT: (C)2005,JPO&NCIPI
申请公布号 JP2005222272(A) 申请公布日期 2005.08.18
申请号 JP20040028998 申请日期 2004.02.05
申请人 SEIKO EPSON CORP 发明人 KANEKO EIJI
分类号 G06F12/16;(IPC1-7):G06F12/16 主分类号 G06F12/16
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