发明名称 |
Clock distribution network with process, supply-voltage, and temperature compensation |
摘要 |
Described are methods and systems for distributing low-skew, predictably timed clock signals. A clock distribution network includes a plurality of dynamically adjustable clock buffers. A control circuit connected to each clock buffer controls the delays through the clock buffers in response to process, voltage, and temperature variations, and consequently maintains a relatively constant signal-propagation delay through the network. In one embodiment, each clock buffer includes skew-offset circuitry that adds to or subtracts from the PVT compensated delay values provided by the PVT control circuit to simplify clock skew minimization.
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申请公布号 |
US2005179479(A1) |
申请公布日期 |
2005.08.18 |
申请号 |
US20050101958 |
申请日期 |
2005.04.08 |
申请人 |
NGUYEN HUY;VU ROXANNE;LAU BENEDICT |
发明人 |
NGUYEN HUY;VU ROXANNE;LAU BENEDICT |
分类号 |
G06F1/10;H03K5/00;H03K5/13;(IPC1-7):G06F1/04 |
主分类号 |
G06F1/10 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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