| 摘要 |
PROBLEM TO BE SOLVED: To provide a charge pump circuit which can reduce voltage loss by a threshold Vth of an FET to a minimum and which can, thereby, take a larger current than that in prior art. SOLUTION: When the clock CLK of an input terminal 1 is a voltage VDD, the voltage 3VDD outputted from a sub-step-up circuit SV is added to a capacitor C1 via an FET-D1, and the capacitor C1 is, thereby, charged by the 3VDD. Then, when the clock CLK becomes ground level, one end of the capacitor C1 becomes 4VDD, and a capacitor C2 is charged by the voltage 4VDD via an FET-D2. Then, when the clock CLK again becomes the voltage VDD, the one end of the capacitor C2 becomes voltage 5VDD, and a capacitor C3 (not shown) is charged by this voltage 5VDD. Hereinafter, the operation is repeated. COPYRIGHT: (C)2005,JPO&NCIPI
|
