| 摘要 |
An integrated semiconductor circuit having a first and a second portion of a substrate, in which a power semiconductor circuit structure and a logic circuit structure are respectively formed. The metallization having a power metal layer and an in relative terms thinner logic metal layer, the two metal layers being located directly above one another in this order, without an intermetal dielectric between them, only in the first portion above the power semiconductor circuit structure, and an uninterrupted conductive barrier layer being located at least between the power metal layer and the intermediate oxide layer and also between the power metal layer and the contact regions and electrode portions of the power semiconductor circuit structure which it contact-connects, and to a method for fabricating it.
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