| 摘要 |
<p><P>PROBLEM TO BE SOLVED: To restore a state of an I/O port after system reset release at high speed without performing arbitration on a bus. <P>SOLUTION: This I/O port control system 1αhaving a CPU 200 and an I/O port circuit 100 on the bus BU has an MRAM (a magnetoresistive memory) 500 as a nonvolatile memory connected to the I/O port circuit 100, storing state data on the I/O port. The I/O port circuit 100 has: a CPU interface part 10; a memory interface part 30; a timing control part 40; and an I/O port control part 20 reading the state data on the I/O port just before system reset from the MRAM 500 through the memory interface part 30 at the time of the system reset release, on the basis of timing control of the timing control part 40, and setting the state of the I/O port on the basis of the state data on the I/O port. <P>COPYRIGHT: (C)2005,JPO&NCIPI</p> |
