发明名称 Quad state logic design methods, circuits, and systems
摘要 Quad-state logic elements and quad-state memory elements are used to reduce the wiring density of integrated circuits. The resulting reduction in wiring interconnects between memories and logic elements results in higher speed, higher density, and lower power integrated circuit designs.
申请公布号 US2005179462(A1) 申请公布日期 2005.08.18
申请号 US20050103782 申请日期 2005.04.11
申请人 WHETSEL LEE D. 发明人 WHETSEL LEE D.
分类号 H03K19/00;(IPC1-7):H03K19/02 主分类号 H03K19/00
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