发明名称
摘要 <p>A semiconductor memory device according to he present invention comprises a first conductivity-type semiconductor substrate in which a second conductivity-type well is formed, a memory cell array composed of a plurality of memory cells arranged in a matrix in the second conductivity-type well, and a substrate voltage control circuit selectively outputting an output voltage to the substrate according to an external input signal.</p>
申请公布号 JP3683915(B2) 申请公布日期 2005.08.17
申请号 JP19940119231 申请日期 1994.05.31
申请人 发明人
分类号 H01L21/66;G11C16/02;G11C16/04;G11C16/06;G11C16/30;G11C17/00;G11C29/00;G11C29/04;G11C29/34;H01L21/8247;H01L27/10;H01L27/105;H01L27/115;H01L29/788;H01L29/792;(IPC1-7):G11C29/00 主分类号 H01L21/66
代理机构 代理人
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