| 摘要 |
A scan-path flip-flop circuit for an integrated circuit memory comprises a number of successively arranged flip-flops. Each flip-flop comprises a master latching circuit for latching a first signal supplied from an associated input terminal of the integrated circuit memory in response to a normal-mode clock signal, supplying the latched first signal to the integrated circuit memory, and further latching a second signal in response to a first scan-mode clock signal. The first signal from the master latching circuit is latched in a slave latching circuit in response to the normal-mode clock signal, and the second signal from the master latching circuit is latched in the slave latching circuit in response to a second scan-mode dock signal. The slave latching circuit of each preceding flip-flop is connected to the master latching circuit of a succeeding flip-flop for shifting the second signal in response to the first scan-mode clock signal. <IMAGE> |
