发明名称 Image memory architecture for achieving high speed access
摘要 An image memory (12) is composed of a memory cell array (27), first and second area selecting circuits (22, 25), and a write circuit (23, 26). The memory cell array includes memory elements (33) arrayed in rows and columns, each of the memory elements (33) being adapted to store pixel data. The first area selecting circuit (22) is adapted to select a plurality of row addresses at the same time, and the second area selecting circuit (25) is adapted to select a plurality of column addresses at the same time. The write circuit (23, 26) is adapted to write same pixel data into selected memory elements out of the memory elements (33), the selected memory elements being associated with the selected row addresses and column addresses. <IMAGE>
申请公布号 EP1564746(A2) 申请公布日期 2005.08.17
申请号 EP20050100940 申请日期 2005.02.10
申请人 NEC ELECTRONICS CORPORATION 发明人 FURIHATA, HIROBUMI;SHIODA, JUNYOU
分类号 G11C8/10;G09G5/391;G09G5/393;G09G5/395;(IPC1-7):G11C8/10 主分类号 G11C8/10
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