发明名称 METHOD AND APPARATUS EMPLOYING INTEGRATED METROLOGY FOR IMPROVED DIELECTRIC ETCH EFFICIENCY
摘要 A method and apparatus for processing a semiconductor wafer is provided for reducing dimensional variation by feeding forward information relating to photoresist mask CD and profile and underlying layer thickness measured at several points on the wafer to adjust the next process the inspected wafer will undergo (e.g., the etch process). After the processing step, dimensions of a structure formed by the process, such as the CD and depth of a trench formed by the process, are measured at several points on the wafer, and this information is fed back to the process tool to adjust the process for the next wafer to further reduce dimensional variation. In certain embodiments, the CD, profile, thickness and depth measurements, etch processing and post-etch cleaning are performed at a single module in a controlled environment. All of the transfer and processing steps performed by the module are performed in a clean environment, thereby increasing yield by avoiding exposing the wafer to the atmosphere and possible contamination between steps.
申请公布号 EP1563532(A2) 申请公布日期 2005.08.17
申请号 EP20030781856 申请日期 2003.11.10
申请人 APPLIED MATERIALS, INC. 发明人 LYMBEROPOULOS, DIMITRIS;HSUEH, GARY;MOHAN, SUKESH
分类号 H01L21/66;(IPC1-7):H01L21/66 主分类号 H01L21/66
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