Apparatus and methods for sharing cache among processors

摘要

A processing system including a plurality of processors, a cache data array, and a crossbar interface connecting the processors with the cache data array. Each processor includes a tag array mapped to the cache data array. In another embodiment, the cache data array includes a plurality of sub-arrays accessible via a plurality of ports of the crossbar interface. The system allows an upper-level cache data array to be shared among processors while cache latency is reduced.