| 摘要 |
A method of enhancing the testability of CMOS ICs, in one or more of the following ways: by minimizing performance degradation of CMOS ICs under test; by eliminating the need for external voltage and current references; by inducing responsive effects; and by minimizing the amount of space used to integrate on-chip testing devices. The device is a CMOS IC comprising a fixed supply voltage, a negative power supply voltage, at least one pair of electrical nodes, and at least one fault-injector. The fault-injector is a transistor comprising a gate for operating in on-state and off-state conditions, and a source node and a drain node for completing an electrical path between a pair of electrical nodes. In an off-state condition, the fault-injector does not interfere with the normal operations of the circuit. However, in an on-state condition, it induces various responsive effects by varying the level of resistance.
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