发明名称 |
Controller for multiple instruction thread processors |
摘要 |
A mechanism controls a multi-thread processor so that when a fist thread encounters a latency event to a first predefined time interval temporary control is transferred to an alternate execution thread for duration of the first predefined time interval and then back to the original thread. The mechanism grants full control to the alternate execution thread when a latency event for a second predefined time interval is encountered. The first predefined time interval is termed short latency event whereas the second time interval is termed long latency event.
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申请公布号 |
US6931641(B1) |
申请公布日期 |
2005.08.16 |
申请号 |
US20000542206 |
申请日期 |
2000.04.04 |
申请人 |
INTERNATIONAL BUSINESS MACHINES CORPORATION |
发明人 |
DAVIS GORDON TAYLOR;HEDDES MARCO C.;LEAVENS ROSS BOYD;VERPLANKEN FABRICE JEAN |
分类号 |
G06F9/46;G06F9/38;G06F9/48;G06F9/52;G06F15/16;(IPC1-7):G06F9/00 |
主分类号 |
G06F9/46 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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