发明名称 Feature targeted inspection
摘要 A method of inspecting a subject integrated circuit. A set of historical integrated circuits is inspected to detect defects and produce historical data. Features of the historical integrated circuits that have an occurrence of defects that is greater than a given limit are designated as high risk features, based on the historical data. Locations of the high risk features are identified on the subject integrated circuit. The locations of the high risk features are input into an inspection tool, and the locations of the high risk features on the integrated circuit are inspected to at least one of detect defects and measure critical dimensions, and produce subject data.
申请公布号 US6931297(B1) 申请公布日期 2005.08.16
申请号 US20040794225D 申请日期 2004.03.05
申请人 LSI LOGIC CORPORATION 发明人 MADGE ROBERT
分类号 G03F7/20;G06F19/00;(IPC1-7):G06F19/00 主分类号 G03F7/20
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