| 摘要 |
PROBLEM TO BE SOLVED: To provide a memory circuit of a high-speed specification which can shorten test time and also can output contents of reading abnormality. SOLUTION: This memory circuit is provided with a circuit for reading first and second data from a memory cell according to an address signal fetched in synchronization with a clock to store them in first and second registers, and an output circuit for outputting the first and second data stored in the first and second registers corresponding to one-cycle rising/falling of the clock. This memory circuit is further provided with a data determination circuit for detecting coincidence/noncoincidence corresponding to each bit of two data units stored in the first and second registers, and a test circuit for outputting the coincidence/noncoincidence signal of the data determination circuit through the output circuit corresponding to one cycle of the clock. COPYRIGHT: (C)2005,JPO&NCIPI
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