发明名称 |
DATA SAMPLING CLOCK EDGE PLACEMENT TRAINING FOR HIGH SPEED GPU-MEMORY INTERFACE |
摘要 |
Circuits, methods, and apparatus for training a phase shift circuit to provide a phase shift for improved date recovery. A specific embodiment of the present invention provides a variable delay cell. A delay through the variable delay cell is changed while training patterns are received. The presence of errors in the received data pattern is tracked, and from the presence or absence of errors a preferred delay is selected and used for receiving data. |
申请公布号 |
WO2005072355(A2) |
申请公布日期 |
2005.08.11 |
申请号 |
WO2005US02432 |
申请日期 |
2005.01.26 |
申请人 |
NVIDIA CORPORATION;KU, TING-SHENG;SHAIKH, ASHFAQ, R. |
发明人 |
KU, TING-SHENG;SHAIKH, ASHFAQ, R. |
分类号 |
G06F13/16;G06F13/42;G11C13/00;H04L7/033 |
主分类号 |
G06F13/16 |
代理机构 |
|
代理人 |
|
主权项 |
|
地址 |
|