| 摘要 |
A nonvolatile memory device using a hybrid switch cell comprises a plurality of hybrid switch cell arrays each having a hierarchical bit line structure including a main bit line and a sub bit line. In the nonvolatile memory device, each sub cell array having the hierarchical bit line structure including a main bit line and a sub bit line is provided as a cross point cell array that comprises a nonvolatile ferroelectric capacitor and a hybrid switch which does not require an additional gate control signal, thereby reducing the whole memory size.
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