| 摘要 |
In a shift register of the present invention, each of flip-flops has a phase difference detection section and a waveform timing forming section as a malfunction prevention circuit. The phase difference detection section detects an overlapping waveform caused by a phase difference between clock signals SCK and SCKB, and generates an output signal A (A 1 , A 2 , . . . ) from which the overlapping portions are removed. The waveform timing forming section outputs an output signal X (X 1 , X 2 , . . . ) obtained by extracting a period when the output signal A (A 1 , A 2 , . . . ) generated in a corresponding phase difference detection section is High, when an output signal Q (Q 1 , Q 2 , . . . ) from a corresponding flip-flop is High. The output signal X (X 1 , X 2 , . . . ) sets a flip-flop in a following stage. According to the above arrangement, it is possible to realize a shift register which does not malfunction and functions properly even in cases where two clock signals SCK and SCKB inputted to the shift register and having different phases from each other are out of phase. It is also possible to realize a display device having the shift register.
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