| 摘要 |
Disclosed herein is a method of forming metal wirings of semiconductor devices a lower metal wiring is formed in a dual damascene pattern formed in an interlayer insulating film and is etched as much as a given thickness of the interlayer insulating film, thereby exposing the top of the lower metal wiring. A via plug is then formed on the exposed top of the lower metal wiring. Accordingly, even if alignment error is generated, increases of resistance, which is caused by contact of the via plug and the lower metal wiring through the sidewall of the projected lower metal wiring, can be prevented. Furthermore, reliability of a process and electrical properties of the devices can be improved.
|
