发明名称 |
Histogram performance counters for use in transaction latency analysis |
摘要 |
Methods and apparatus are described for measuring latency in computer systems. A computer system includes a processor, memory, and I/O. The processor is operable to initiate transactions involving the memory and the I/O. The computer system further includes a latency counter operable to measure a latency for each of selected ones of the transactions. The system also includes a plurality of histogram counters. Each histogram counter is operable to count the latencies corresponding to an associated latency range.
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申请公布号 |
US2005177344(A1) |
申请公布日期 |
2005.08.11 |
申请号 |
US20040775974 |
申请日期 |
2004.02.09 |
申请人 |
NEWISYS, INC. A DELAWARE CORPORATION |
发明人 |
KHALEEL ADNAN |
分类号 |
G06F11/30;(IPC1-7):G06F11/30 |
主分类号 |
G06F11/30 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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