| 摘要 |
A clock generation circuit comprising two programmable ring oscillators (10, 20) arranged and configured to operate in a mutually exclusive manner, and a variable programmable delay element (not shown). An input programming pattern (14) is provided as an input to the oscillating circuit, the programming pattern (14) providing data representative of the sequence of frequencies at which the clock signal is required to be generated. The outputs of both the oscillators (10, 20) are connected to a clock switch (16), from which the generated clock signal (18) is output. When a request fro a change of frequency is received, the currently idle oscillator (20) is first activated with the next required frequency, the output of the currently operative oscillator (10) is then gated when the clock signal thereof goes low. Next, the previously gated output of oscillator (20) is ungated when its output goes low, and then oscillator (10) is de-activated. |
