| 摘要 |
A display controller includes a frame memory, an interrupt output cycle setting register, and an interrupt signal generation section. The frame memory stores the display data for at least one vertical scan period, the display data being supplied from a host. An output cycle of an interrupt signal to be output to the host is set in units of one vertical scan period in the interrupt output cycle setting register. The interrupt signal generation section outputs an interrupt signal having pulses in the output cycle set in the interrupt output cycle setting register to the host as the interrupt signal. The display controller stores the display data supplied from the host corresponding to the interrupt signal in the frame memory, reads the display data from the frame memory in a predetermined read cycle, and supplies the display data to the data driver.
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