| 摘要 |
<P>PROBLEM TO BE SOLVED: To provide a three-dimensional semiconductor device of chip multilayer structure capable of loading the memory LSI chip of a large size and a large capacity, and obtaining an SOC-quality high performance. <P>SOLUTION: A spacer chip 16 is interposed between the logic LSI chip 14 of a lower stage and the memory LSI chip 15 of an upper stage, and many via-holes 17.... and connection wiring layers 18... are formed on the spacer chip 16. Respective lower stage wiring and upper stage wiring are flip-chip (gold bump) connected through the via-holes 17.... and the connection wiring layers 18... of the spacer chip 16 in one-to-one correspondence, in a corresponding relationship between a lower stage wiring group formed on the upper surface of the logic LSI chip 14 and an upper stage wiring group formed on the lower surface of the memory LSI chip 15. <P>COPYRIGHT: (C)2005,JPO&NCIPI |
